PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Azémard, Nadine"

Author of the publication

copydeleteadd this publication to your clipboard
Statistical timing characterization.

, , , and . ISSoC, page 1-4. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nadine Böpple University of Stuttgart

Nadine Schnabel University of Stuttgart

Nadine Koch University of Stuttgart

Nadine Lahn University of Stuttgart

Nadine Thiele University of Stuttgart

 

Other publications of authors with the same name

Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014., and . J. Low Power Electronics, 11 (2): 249 (2015)P.SIZE: a sizing aid for optimized designs., , and . EURO-DAC, page 160-165. IEEE Computer Society Press, (1992)Delay bound based CMOS gate sizing technique., , , , and . ISCAS (5), page 189-192. IEEE, (2004)Statistical Characterization of Library Timing Performance., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic., , , , and . ICRC, page 1-6. IEEE, (2017)Product On-Chip Process Compensation for Low Power and Yield Enhancement., , , , , , , , , and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)Gate Sizing for Low Power Design., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 301-312. Kluwer, (2001)Statistical timing characterization., , , and . ISSoC, page 1-4. IEEE, (2012)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1677-1684 (2006)Circuit sizing method under delay constraint., , , and . ISCAS, IEEE, (2006)