Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Statistical Characterization of Library Timing Performance.

V. Migairou, R. Wilson, S. Engels, N. Azémard, and P. Maurine. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nadine Böpple University of Stuttgart

Nadine Schnabel University of Stuttgart

Nadine Koch University of Stuttgart

Nadine Lahn University of Stuttgart

Nadine Thiele University of Stuttgart

Other publications of authors with the same name

Delay bound based CMOS gate sizing technique.A. Verle, X. Michel, P. Maurine, N. Azémard, and D. Auvergne. ISCAS (5), page 189-192. IEEE, (2004)P.SIZE: a sizing aid for optimized designs.N. Azémard, V. Bonzom, and D. Auvergne. EURO-DAC, page 160-165. IEEE Computer Society Press, (1992)Statistical Characterization of Library Timing Performance.V. Migairou, R. Wilson, S. Engels, N. Azémard, and P. Maurine. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014.N. Azémard, and E. García-Moreno. J. Low Power Electronics, 11 (2): 249 (2015)Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic.N. Jeanniot, G. Pillonnet, P. Nouet, N. Azémard, and A. Todri-Sanial. ICRC, page 1-6. IEEE, (2017)Product On-Chip Process Compensation for Low Power and Yield Enhancement.N. Moubdi, P. Maurine, R. Wilson, N. Azémard, V. Dumettier, A. Bansal, S. Barasinski, A. Tournier, G. Durieu, D. Meyer and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)Circuit sizing method under delay constraint.A. Verle, A. Landrault, P. Maurine, and N. Azémard. ISCAS, IEEE, (2006)Logical effort model extension to propagation delay representation.B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azémard, and D. Auvergne. IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1677-1684 (2006)Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015.R. Reis, and N. Azémard. J. Low Power Electronics, 12 (1): 56-57 (2016)Performance Metric Based Optimization Protocol.X. Michel, A. Verle, P. Maurine, N. Azémard, and D. Auvergne. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 100-109. Springer, (2004)