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Fault injection acceleration by architectural importance sampling., , , and . CODES+ISSS, page 212-219. IEEE, (2015)Aging-Aware Design of Microprocessor Instruction Pipelines., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (5): 704-716 (2014)Stress-aware P/G TSV planning in 3D-ICs., , , and . ASP-DAC, page 94-99. IEEE, (2015)Chip-level modeling and analysis of electrical masking of soft errors., , , and . VTS, page 1-6. IEEE Computer Society, (2013)Defects and Faults in Quantum Cellular Automata at Nano Scale., , , and . VTS, page 291-296. IEEE Computer Society, (2004)Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation., and . European Test Symposium, page 1-6. IEEE Computer Society, (2012)Re-using BIST for circuit aging monitoring., , , , , and . ETS, page 1-2. IEEE, (2015)Protecting caches against multi-bit errors using embedded erasure coding., , , , and . ETS, page 1-6. IEEE, (2015)Representative critical-path selection for aging-induced delay monitoring., , , and . ITC, page 1-10. IEEE Computer Society, (2013)High-level aging estimation for FPGA-mapped designs., and . FPL, page 284-291. IEEE, (2012)