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Disambiguation of "Choudhury, Mihir R."

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Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures.

, , , and . DAC, page 48:1-48:8. ACM, (2013)

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R. Leister

R. Koerner

R. Watty

Univ. -Prof. Dr. -Ing. Jörg Roth-Stielow University of Stuttgart

LETSCOPE : Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics, , , , , , , , , and 3 other author(s). IEEE EUROCON 2023 : 20th International Conference on Smart Technologies, page 665-670. IEEE, (2023)

Julian Raible University of Stuttgart

Artificial Neural Network Guided Compensation of Nonlinear Payload and Wear Effects for Industrial Robots, , , , , , , , , and . 2023 IEEE 19th International Conference on Automation Science and Engineering (CASE), IEEE, (2023)
 

Other publications of authors with the same name

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (10): 1517-1530 (2014)Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits., , and . European Test Symposium, page 179-184. IEEE Computer Society, (2008)Technology exploration for graphene nanoribbon FETs., , , and . DAC, page 272-277. ACM, (2008)Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (5): 820-831 (2016)Masking timing errors on speed-paths in logic circuits., and . DATE, page 87-92. IEEE, (2009)Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion., , and . J. Electronic Testing, 25 (2-3): 197-207 (2009)Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques., , and . ICCAD, page 204-209. ACM, (2006)Approximate logic circuits for low overhead, non-intrusive concurrent error detection., and . DATE, page 903-908. ACM, (2008)Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience., , , and . IEEE Trans. Computers, 63 (2): 497-509 (2014)Bi-decomposition of large Boolean functions using blocking edge graphs., and . ICCAD, page 586-591. IEEE, (2010)