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Disambiguation of "Muralimanohar, Naveen"

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Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories.

, , , , and . TACO, 11 (4): 40:1-40:25 (2014)

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Other publications of authors with the same name

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads., , , , and . HPCA, page 41-52. IEEE Computer Society, (2012)CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory., , , , , and . DATE, page 33-38. IEEE, (2012)Design trade-offs for high density cross-point resistive memory., , , , and . ISLPED, page 209-214. ACM, (2012)Improving memristor memory with sneak current sharing., , , and . ICCD, page 549-556. IEEE Computer Society, (2015)Near-Memory Data Services., , , , , , , , , and 1 other author(s). IEEE Micro, 36 (1): 6-13 (2016)Interconnect design considerations for large NUCA caches., and . ISCA, page 369-380. ACM, (2007)LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems., , , , and . ISCA, page 285-296. IEEE Computer Society, (2012)Rethinking DRAM design and organization for energy-constrained multi-cores., , , , , and . ISCA, page 175-186. ACM, (2010)Understanding the trade-offs in multi-level cell ReRAM memory design., , , , and . DAC, page 108:1-108:6. ACM, (2013)CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models., , , and . IEEE Trans. VLSI Syst., 23 (7): 1254-1267 (2015)