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Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.

F. Carbognani, F. Bürgin, N. Felber, H. Kaeslin, and W. Fichtner. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 446-455. Springer, (2005)

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Hon. -Prof. Dr. -Ing. Hubert Ehbing University of Stuttgart

Dr. Hubert Keller University of Stuttgart

PD Dr. -Ing. Hubert Effenberger University of Stuttgart

Hubert Fußhoeller University of Stuttgart

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Design and Verification of a Stack Processor Virtual Component.M. Stadler, M. Thalmann, T. Röwer, H. Kaeslin, N. Felber, and W. Fichtner. IEEE Micro, 21 (2): 69-80 (2001)SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.M. Gautschi, M. Muehlberghuber, A. Traber, S. Stucki, M. Baer, R. Andri, L. Benini, B. Muheim, and H. Kaeslin. ASAP, page 25-29. IEEE Computer Society, (2014)Compressive sensing for WiFi-based passive bistatic radar.P. Maechler, N. Felber, and H. Kaeslin. EUSIPCO, page 1444-1448. IEEE, (2012)Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.M. Schaffner, F. Gürkaynak, P. Greisen, H. Kaeslin, L. Benini, and A. Smolic. IEEE Trans. Circuits Syst. Video Techn., 26 (11): 2093-2108 (2016)A 2 Gb/s balanced AES crypto-chip implementation.F. Gürkaynak, A. Burg, N. Felber, W. Fichtner, D. Gasser, F. Hug, and H. Kaeslin. ACM Great Lakes Symposium on VLSI, page 39-44. ACM, (2004)VINCI: Secure Test of a VLSI High-Speed Encryption System.H. Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, R. Zimmermann, and W. Fichtner. ITC, page 782-790. IEEE Computer Society, (1993)Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX.H. Kaeslin. it - Informationstechnik, 30 (1): 11-16 (1988)Waveform coding for low-power digital filtering of speech data.J. Wassner, H. Kaeslin, N. Felber, and W. Fichtner. IEEE Trans. Signal Processing, 51 (6): 1656-1661 (2003)Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.P. Greisen, M. Schaffner, S. Heinzle, M. Runo, A. Smolic, A. Burg, H. Kaeslin, and M. Gross. IEEE Trans. Circuits Syst. Video Techn., 22 (11): 1577-1589 (2012)42% power savings through glitch-reducing clocking strategy in a hearing aid application.F. Carbognani, F. Bürgin, N. Felber, H. Kaeslin, and W. Fichtner. ISCAS, IEEE, (2006)