Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable multi-processor SoC for media applications.

M. Zhu, L. Liu, S. Yin, Y. Wang, W. Wang, and S. Wei. ISCAS, page 2011-2014. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wei Yu University of Stuttgart

Li-Wei Chen University of Stuttgart

Daniel Weiskopf

Stefanie Weidner

Other publications of authors with the same name

Affine transformations for communication and reconfiguration optimization of loops on CGRAs.D. Liu, S. Yin, L. Liu, and S. Wei. ISCAS, page 2541-2544. IEEE, (2013)Energy-efficient stream task scheduling scheme for embedded multimedia applications on multi-issued stream architectures.S. Cao, Z. Li, F. Wang, G. Jiang, Z. Chen, and S. Wei. Journal of Systems Architecture - Embedded Systems Design, 59 (4-5): 187-201 (2013)Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor.L. Liu, Y. Chen, D. Wang, S. Yin, X. Wang, L. Wang, H. Lei, P. Cao, and S. Wei. SCIENCE CHINA Information Sciences, 57 (8): 1-14 (2014)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.Y. Wang, L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, and S. Wei. SCIENCE CHINA Information Sciences, 56 (11): 1-20 (2013)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system.L. Liu, Y. Chen, S. Yin, L. Zhou, H. Yuan, and S. Wei. SCIENCE CHINA Information Sciences, 57 (8): 1-14 (2014)Acceleration of Nested Conditionals on CGRAs via Trigger Scheme.S. Yin, P. Zhou, L. Liu, and S. Wei. ICCAD, page 597-604. IEEE, (2015)Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.S. Yin, D. Liu, L. Liu, S. Wei, and Y. Guo. DATE, page 115-120. ACM, (2015)Reconfigurable computing - evolution of Von Neumann architecture.S. Wei. FPT, IEEE, (2010)A power-efficient network-on-chip for multi-core stream processors.G. Jiang, F. Wang, Z. Li, and S. Wei. ASICON, page 1-4. IEEE, (2013)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.H. Luo, S. Wei, D. Chen, and D. Guo. J. Parallel Distrib. Comput., 74 (9): 2818-2830 (2014)

PUMA

Disambiguation of "Wei, Shaojun"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable multi-processor SoC for media applications.

Please choose a person to relate this publication to

Wei Yu University of Stuttgart

Li-Wei Chen University of Stuttgart

Daniel Weiskopf

Stefanie Weidner

Stefanie Weidner

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A reconfigurable multi-processor SoC for media applications.

Please choose a person to relate this publication to

Wei Yu University of Stuttgart

Li-Wei Chen University of Stuttgart

Daniel Weiskopf

Stefanie Weidner

Stefanie Weidner

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A reconfigurable multi-processor SoC for media applications.