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A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.

, , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 748-752 (2011)

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A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs., , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 748-752 (2011)A Background DAC Error Estimation in Sigma-Delta ADCs using a Pseudo Random Noise based Correlation Technique., and . ISCAS, page 1549-1552. IEEE, (2009)An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal., , , , and . ISCAS, page 73-76. IEEE, (2012)Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs., , and . ISCAS, page 2167-2170. IEEE, (2010)Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters., and . IEEE Trans. on Circuits and Systems, 57-I (7): 1500-1512 (2010)An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR., , , and . J. Solid-State Circuits, 46 (12): 2869-2881 (2011)An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization., , , and . ISSCC, page 472-474. IEEE, (2011)A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW., , , , and . ISSCC, page 154-156. IEEE, (2012)A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW., , , , , and . J. Solid-State Circuits, 49 (2): 392-404 (2014)