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Disambiguation of "Kauffman, John G."

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A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.

, , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 748-752 (2011)

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G. Daiß

G. Wagner

John Nixon University of Stuttgart

Isaac Henderson Johnson Jeyakumar University of Stuttgart

David John Cross University of Stuttgart

 

Other publications of authors with the same name

A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs., , , and . IEEE Trans. on Circuits and Systems, 58-II (11): 748-752 (2011)Low power quantizer design in CT Delta Sigma modulators., , , , and . ISCAS, page 1990-1993. IEEE, (2013)An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR., , , and . J. Solid-State Circuits, 46 (12): 2869-2881 (2011)An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization., , , and . ISSCC, page 472-474. IEEE, (2011)Integrator swing reduction in feedback compensated Sigma-Delta modulators., , , and . ISCAS, page 2026-2029. IEEE, (2013)A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW., , , , and . ISSCC, page 154-156. IEEE, (2012)A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW., , , , , and . J. Solid-State Circuits, 49 (2): 392-404 (2014)A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection., , , and . J. Solid-State Circuits, 51 (3): 660-670 (2016)A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators., , , and . ICECS, page 1-4. IEEE, (2021)A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC., , and . ISCAS, page 3138-3141. IEEE, (2012)