Author of the publication

Efficient built-in self-test for video coding cores: A case study on motion estimation computing array.

, , and . APCCAS, page 1751-1754. IEEE, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications., , , and . DFT, page 136-143. IEEE Computer Society, (2010)A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip., and . DFT, page 122-128. IEEE Computer Society, (2010)Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM., , , , , , , and . Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications., , and . IEICE Transactions, 89-A (2): 377-384 (2006)A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications., and . Signal Processing Systems, 52 (3): 211-229 (2008)Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits., , and . IEEE Trans. Instrumentation and Measurement, 58 (7): 2196-2208 (2009)Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays., , and . IEEE Trans. VLSI Syst., 18 (2): 319-324 (2010)Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder., , , and . IEEE Trans. Computers, 60 (5): 628-638 (2011)Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs., , , , , , and . Asian Test Symposium, page 107-108. IEEE Computer Society, (2013)High-performance 3D-SRAM architecture design., and . APCCAS, page 907-910. IEEE, (2010)