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Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

B. Bai, C. Hsu, M. Wu, C. Chen, Y. Chen, K. Luo, L. Cheng, and J. Li. Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)

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Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.H. Geng, J. Liu, J. Liu, P. Luo, L. Cheng, S. Grant, and Y. Shi. Integration, (2016)Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.P. Luo, J. Chen, C. Wey, L. Cheng, J. Chen, and W. Wu. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (11): 2097-2101 (2008)Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.S. Wei, Y. Lee, C. Ho, C. Sun, and L. Cheng. VLSI-DAT, page 1-4. IEEE, (2013)Benchmarking for research in power delivery networks of three-dimensional integrated circuits.P. Luo, C. Zhang, Y. Chang, L. Cheng, H. Lee, B. Sheu, Y. Su, D. Kwai, and Y. Shi. ISPD, page 17-24. ACM, (2013)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, and Y. Chu. IEEE Trans. on Circuits and Systems, 61-II (12): 947-951 (2014)Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.B. Bai, C. Hsu, M. Wu, C. Chen, Y. Chen, K. Luo, L. Cheng, and J. Li. Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)Variation aware optimal threshold voltage computation for on-chip noise sensors.T. Wang, C. Zhang, J. Xiong, P. Luo, L. Cheng, and Y. Shi. ICCAD, page 205-212. IEEE, (2014)On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.T. Wang, C. Zhang, J. Xiong, P. Luo, L. Cheng, and Y. Shi. IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (10): 1744-1754 (2016)Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.C. Chou, Y. Lai, Y. Chang, C. Wang, L. Cheng, S. Huang, and S. Chang. IEEE Trans. on CAD of Integrated Circuits and Systems, 36 (1): 146-155 (2017)Incremental transient simulation of power grid.C. Ho, Y. Lee, S. Wei, and L. Cheng. ISPD, page 93-100. ACM, (2014)

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Disambiguation of "Cheng, Liang-Chia"

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Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

Please choose a person to relate this publication to

Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Cheng, Liang-Chia"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

Please choose a person to relate this publication to

Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.