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Disambiguation of "Hwang, Wei"

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Design Of Provably Correct Storage Arrays.

, , and . VLSI Design, page 196-. IEEE Computer Society, (2001)

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Wei Yu University of Stuttgart

Dr. rer. nat. Ran Wei University of Stuttgart

Wei Zhang University of Stuttgart

Li-Wei Chen University of Stuttgart

Fiona Jacqueline Weiß University of Stuttgart

 

Other publications of authors with the same name

A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit., , and . ICCD, page 712-717. IEEE Computer Society, (1997)A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor., and . APCCAS, page 1931-1934. IEEE, (2006)Adaptive Power Control Technique on Power-Gated Circuitries., and . IEEE Trans. VLSI Syst., 19 (7): 1167-1180 (2011)A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist., , , , , , , , , and 1 other author(s). IEEE Trans. on Circuits and Systems, 59-II (12): 863-867 (2012)A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS., , , and . ISLPED, page 291-296. IEEE/ACM, (2011)A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist., , , , , , , , , and 3 other author(s). SoCC, page 218-223. IEEE, (2012)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems., , , , , and . SoCC, page 136-139. IEEE, (2014)Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications., , , , and . VLSI-DAT, page 1-4. IEEE, (2015)A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables., and . J. Solid-State Circuits, 46 (2): 507-519 (2011)A flexible two-layer external memory management for H.264/AVC decoder., , and . SoCC, page 219-222. IEEE, (2007)