Author of the publication

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations.

, , and . Asian Test Symposium, page 303-310. IEEE Computer Society, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Test generation for specification test of analog circuits using efficient test response observation methods., and . Microelectronics Journal, 36 (9): 820-832 (2005)Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits., , and . J. Electronic Testing, 14 (3): 259-272 (1999)On the C-Testability of Generalized Counters., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (5): 713-726 (1987)Performance-Optimized Design for Parametric Reliability., , , , and . J. Electronic Testing, 24 (1-3): 129-141 (2008)Low-Cost Specification Based Testing of RF Amplifier Circuits using Oscillation Principles., , and . J. Electronic Testing, 26 (1): 13-24 (2010)Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications., , , and . J. Electronic Testing, 21 (3): 323-339 (2005)Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization., and . IEEE Trans. Computers, 46 (11): 1208-1218 (1997)Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers., , and . IEEE Trans. VLSI Syst., 17 (6): 803-814 (2009)System-Level Specification Testing Of Wireless Transceivers., , and . IEEE Trans. VLSI Syst., 16 (3): 263-276 (2008)Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic., , and . IEEE Trans. VLSI Syst., 18 (4): 675-679 (2010)