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Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip., , and . IEEE Trans. Computers, 52 (12): 1619-1632 (2003)Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption., , , and . IEEE Trans. Computers, 64 (12): 3335-3347 (2015)Murphy goes 3D.. ISVLSI, page 102. IEEE Computer Socity, (2013)User-constrained test architecture design for modular SOC testing., , , , and . European Test Symposium, page 80-85. IEEE Computer Society, (2004)Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2., and . IEEE Design & Test of Computers, 26 (3): 4 (2009)Wrapper design for embedded core test., , , and . ITC, page 911-920. IEEE Computer Society, (2000)Efficient test access mechanism optimization for system-on-chip., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (5): 635-643 (2003)Contactless testing: Possibility or pipe-dream?, , , , , , and . DATE, page 676-681. IEEE, (2009)Efficient Wrapper/TAM Co-Optimization for Large SOCs., , and . DATE, page 491-498. IEEE Computer Society, (2002)A structured and scalable test access architecture for TSV-based 3D stacked ICs., , and . VTS, page 269-274. IEEE Computer Society, (2010)