PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Pan, David Z."

Author of the publication

copydeleteadd this publication to your clipboard
Keep it straight: teaching placement how to better handle designs with datapaths.

, , , , , , and . ISPD, page 79-86. ACM, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Qi Pan University of Stuttgart

Xiny Pan University of Stuttgart

Dr. Marie Davidova University of Stuttgart

Karthik Pandaram University of Stuttgart

Jiaxin Pan University of Stuttgart

 

Other publications of authors with the same name

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 185-196 (2010)Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 905-917 (2013)Skew Management of NBTI Impacted Gated Clock Trees., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (6): 918-927 (2013)Machine learning and pattern matching in physical design., , , and . ASP-DAC, page 286-293. IEEE, (2015)Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC., , , , and . ICCAD, page 563-570. IEEE Computer Society, (2011)Chemical-mechanical polishing aware application-specific 3D NoC design., , , and . ICCAD, page 207-212. IEEE Computer Society, (2011)A high-performance triple patterning layout decomposer with balanced density., , , , , and . ICCAD, page 163-169. IEEE, (2013)Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction., and . ISQED, page 79-84. IEEE Computer Society, (2006)Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization., , , , , , , and . IEEE Trans. VLSI Syst., 26 (9): 1613-1626 (2018)Total power optimization combining placement, sizing and multi-Vt through slack distribution management., , and . ASP-DAC, page 352-357. IEEE, (2008)