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Disambiguation of "Huhn, Sebastian"

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Enhancing robustness of sequential circuits using application-specific knowledge and formal methods.

, , , and . ASP-DAC, page 182-187. IEEE, (2017)

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Sebastian Höpfl University of Stuttgart

Bayesian modelling of time series data (BayModTS)—a FAIR workflow to process sparse and highly variable data, , , , , , , , , and 1 other author(s). Bioinformatics, 40 (5): btae312 (May 2024)

Sebastian Friedl University of Stuttgart

Communication extension for cloud-based machine control of simulated robot processes, , , and . 2016 IEEE International Conference on Industrial Technology (ICIT), page 54-58. (March 2016)

Sebastian Brandhofer University of Stuttgart

Sebastian Haunss

Dr. Sebastian Rojek University of Stuttgart

 

Other publications of authors with the same name

Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns., , and . ETS, page 1-2. IEEE, (2019)Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips, , , , , and . 2023 IEEE European Test Symposium (ETS), IEEE, (2023)Ein KI-Verfahren für das Kartenspiel Magic: The Gathering., , , , , and . Informatiktage, volume S-5 of LNI, page 25-28. GI, (2007)Ein KI-Verfahren für das Kartenspiel Magic: The Gathering., , , , , and . Informatik Spektrum, 31 (3): 241-248 (2008)Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits., , , and . IEEE Trans. VLSI Syst., 27 (4): 875-887 (2019)Reconfigurable TAP controllers with embedded compression for large test data volume., , and . DFT, page 1-6. IEEE Computer Society, (2017)Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems., , , and . LDIC, page 400-405. Springer, (2018)Exploring superior structural materials using multi-objective optimization and formal techniques., , , , and . ISED, page 13-17. IEEE, (2016)Enhancing robustness of sequential circuits using application-specific knowledge and formal methods., , , and . ASP-DAC, page 182-187. IEEE, (2017)SAT-Lancer: A Hardware SAT-Solver for Self-Verification., , , and . ACM Great Lakes Symposium on VLSI, page 479-482. ACM, (2018)