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Exploring superior structural materials using multi-objective optimization and formal techniques.

, , , , and . ISED, page 13-17. IEEE, (2016)

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SAT-based post-processing for regional capture power reduction in at-speed scan test generation., , and . ETS, page 1-6. IEEE, (2016)A Highly Fault-Efficient SAT-Based ATPG Flow., and . IEEE Design & Test of Computers, 29 (4): 63-70 (2012)Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements., , and . LATS, page 1-4. IEEE, (2019)Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression., , , and . DATE, page 578-583. IEEE, (2017)Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults., , , , , and . MEMOCODE, page 181-187. IEEE Computer Society, (2007)Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques., and . European Test Symposium, page 81-86. IEEE Computer Society, (2009)High Quality Test Pattern Generation and Boolean Satisfiability., and . Springer, (2012)Machine Learning-based Prediction of Test Power., , , and . ETS, page 1-6. IEEE, (2019)Formal Verification on the Word Level using SAT-like Proof Techniques., , , , and . MBMV, page 81-90. Shaker, (2007)SAT-based ATPG for Path Delay Faults in Sequential Circuits., , and . ISCAS, page 3671-3674. IEEE, (2007)