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Disambiguation of "De, Vivek"

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A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors.

, , , , , , , , , , , , and . J. Solid-State Circuits, 54 (12): 3316-3325 (2019)

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Nithyasree Vivekanandham Pushpalatha University of Stuttgart

Ishaan Desai University of Stuttgart

preCICE Distribution Version v2404.0, , , , , , , , , and 14 other author(s). Software, (2024)

Jörg Desel

Das ist Informatik (Eds.) Springer, (2001)

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

 

Other publications of authors with the same name

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS., , , , , and . CICC, page 1-4. IEEE, (2014)Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)Analytical Model for the Propagation Delay of Through Silicon Vias., , , , and . ISQED, page 553-556. IEEE Computer Society, (2008)A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS., , , and . ICCD, page 567-573. IEEE Computer Society, (2005)F1: Designing secure systems: Manufacturing, circuits and architectures., , , , , , and . ISSCC, page 492-494. IEEE, (2016)Resiliency for many-core system on a chip., , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor., , and . ICICDT, page 1-4. IEEE, (2014)Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study., , , , and . CICC, page 1-4. IEEE, (2014)Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating., , , , , , , , and . J. Solid-State Circuits, 52 (1): 50-63 (2017)An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and $V_MIN$ Optimization., , , , , , , , , and 19 other author(s). J. Solid-State Circuits, 54 (1): 144-157 (2019)