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Disambiguation of "Joshi, Rajiv V."

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PD/SOI SRAM performance in presence of gate-to-body tunneling current.

, , , , , , and . IEEE Trans. VLSI Syst., 11 (6): 1106-1113 (2003)

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V. Vaikuntanathan

Jasmin Joshi-Thompson University of Stuttgart

V. Zaverkin

Michael P. Voigt Universität Stuttgart

Wolfgang Vogel

 

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14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation., , , , and . VLSIC, page 268-. IEEE, (2015)Robust bias temperature instability refresh design and methodology for memory cell recovery., , , , and . ICICDT, page 1-4. IEEE, (2014)Efficient analog circuit optimization using sparse regression and error margining., , , , and . ISQED, page 410-415. IEEE, (2016)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectronics Journal, 38 (8-9): 931-941 (2007)Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction"., and . IEEE Trans. VLSI Syst., 23 (7): 1380 (2015)Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. VLSI Syst., 23 (3): 534-543 (2015)Design Considerations and Implementation of a High Performance Dynamic Register File., and . VLSI Design, page 526-531. IEEE Computer Society, (1999)Design Of Provably Correct Storage Arrays., , and . VLSI Design, page 196-. IEEE Computer Society, (2001)Design technology co-optimization for 10 nm and beyond., and . CICC, page 1. IEEE, (2014)Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations., , , , and . ISPASS, page 153-154. IEEE Computer Society, (2016)