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On logic synthesis of conventionally hard to synthesize circuits using genetic programming.

, , , and . DDECS, page 346-351. IEEE Computer Society, (2010)

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Techniques for SAT-based constrained test pattern generation., , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (2): 185-195 (2013)The Case for a Balanced Decomposition Process., and . DSD, page 601-604. IEEE Computer Society, (2009)General Digit-Serial Normal Basis Multiplier with Distributed Overlap., and . DSD, page 94-101. IEEE Computer Society, (2007)On logic synthesis of conventionally hard to synthesize circuits using genetic programming., , , and . DDECS, page 346-351. IEEE Computer Society, (2010)ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction., , and . Microprocessors and Microsystems - Embedded Hardware Design, (2018)Underwater Acoustic Communications in Time-Varying Dispersive Channels., , and . FedCSIS, page 467-474. (2016)Using Voters May Lead to Secret Leakage., , and . DDECS, page 1-4. IEEE, (2019)PBO-Based Test Compression., , and . DSD, page 679-682. IEEE Computer Society, (2014)The Influence of Implementation Technology on Dependability Parameters., , and . DSD, page 368-373. IEEE Computer Society, (2012)SAT-Based Generation of Optimum Function Implementations with XOR Gates., , and . DSD, page 163-170. IEEE Computer Society, (2017)