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SAT-Based Generation of Optimum Function Implementations with XOR Gates.

, , and . DSD, page 163-170. IEEE Computer Society, (2017)

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The influence of implementation type on dependability parameters., , and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (6-7): 641-648 (2013)Multiple-Vector Column-Matching BIST Design Method., and . DDECS, page 268-273. IEEE Computer Society, (2006)Fault Tolerant System Design Method Based on Self-Checking Circuits., , and . IOLTS, page 185-186. IEEE Computer Society, (2006)Survey of the Algorithms in the Column-Matching BIST Method., and . IOLTS, page 181. IEEE Computer Society, (2004)Improving the iterative power of resynthesis., and . DDECS, page 30-33. IEEE, (2012)Asynchronous sum-of-products logic minimization and orthogonalization., , and . I. J. Circuit Theory and Applications, 42 (6): 562-571 (2014)SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support., , , and . Journal of Circuits, Systems, and Computers, 28 (Supplement-1): 1940010:1-1940010:29 (2019)A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms., and . DSD, page 757-764. IEEE Computer Society, (2009)Asynchronous two-level logic of reduced cost., and . DDECS, page 68-73. IEEE Computer Society, (2009)A new method for path criticality calculation., , , and . DDECS, page 190-193. IEEE, (2016)