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Embedded Scan Test with Diagnostic Features for Self-Testing SoCs.

, , , , , and . IOLTS, page 181-182. IEEE Computer Society, (2006)

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On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check., , , and . J. Electronic Testing, 19 (5): 501-510 (2003)Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip., , and . IOLTS, page 183-. IEEE Computer Society, (2003)A Hierarchical Self Test Scheme for SoCs., , and . IOLTS, page 37-44. IEEE Computer Society, (2004)A new method for on-line state machine observation for embedded microprocessors., , and . HLDVT, page 34-39. IEEE Computer Society, (2000)On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check., , , and . IOLTW, page 69-73. IEEE Computer Society, (2002)On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures., , and . IOLTW, page 178. IEEE Computer Society, (2002)Hardware/Software Based Hierarchical Self Test for SoCs., , , , , and . DDECS, page 159-160. IEEE Computer Society, (2006)A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features., , and . IOLTS, page 241-246. IEEE Computer Society, (2005)A Configurable Modular Test Processor and Scan Controller Architecture., , , , and . IOLTS, page 277-284. IEEE Computer Society, (2007)Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes., , and . DSD, page 433-438. IEEE Computer Society, (2006)