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On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.

, , , and . J. Electronic Testing, 19 (5): 501-510 (2003)

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An efficient on-line-test and back-up scheme for embedded processors., , and . ITC, page 964-972. IEEE Computer Society, (1999)On-line fehler-erkennung und schnelle wiederherstellungs-techniken für zuverlässige eingebettete prozessoren.. Ausgezeichnete Informatikdissertationen, volume D-2 of LNI, GI, (2001)A register-transfer-level fault simulator for permanent and transient faults in embedded processors., , , , and . DATE, page 811. IEEE Computer Society, (2001)Generating reliable embedded processors., and . IEEE Micro, 18 (5): 33-41 (1998)On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity., , and . IOLTW, page 51-53. IEEE Computer Society, (2001)Evaluating coverage of error detection logic for soft errors using formal methods., , , , , and . DATE, page 176-181. European Design and Automation Association, Leuven, Belgium, (2006)A Test Processor Concept for Systems-on-a-Chip., , and . ICCD, page 210-. IEEE Computer Society, (2002)On-line Error Detection and Fast Recover Techniques for Dependable Embedded Processors. Lecture Notes in Computer Science Springer, (2002)Control Signal Protection For High Performance Processors., and . IOLTS, page 173-. IEEE Computer Society, (2003)On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check., , , and . J. Electronic Testing, 19 (5): 501-510 (2003)