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Hardware Support for Efficient Resource Utilization in Manycore Processor Systems., , , , , , and . Multiprocessor System-on-Chip, Springer, (2011)Adaptive multi-layer techniques for increased system dependability, , , , , , , , , and 2 other author(s). it - Information Technology, 57 (3): 149-158 (2015)A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV., , , , and . CLOUD, page 950-957. IEEE, (2015)HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation., , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 280-291. Springer, (2013)Efficient Inter-Task Communication in Tiled Many-Core System-on-Chip Architectures.. Technical University Munich, Germany, (2018)Distributed cooperative shared last-level caching in tiled multiprocessor system on chip., , and . DATE, page 1-4. European Design and Automation Association, (2014)Sharer status-based caching in tiled multiprocessor systems-on-chip., , , , and . SpringSim (HPS), page 67-74. SCS/ACM, (2015)An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip., , , and . DSD, page 621-628. IEEE Computer Society, (2015)A SW performance estimation framework for early system-level-design using fine-grained instrumentation., , , , , and . DATE, page 468-473. European Design and Automation Association, Leuven, Belgium, (2006)Dependable task and communication migration in tiled manycore system-on-chip., , , , , and . FDL, page 1-8. IEEE, (2014)