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Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.

, , , , and . DFT, page 298-305. IEEE Computer Society, (2004)

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Reinventing Memory System Design for Many-Accelerator Architecture., , , and . J. Comput. Sci. Technol., 29 (2): 273-280 (2014)Retraining-based timing error mitigation for hardware neural networks., , , , , , , , , and 1 other author(s). DATE, page 593-596. ACM, (2015)Temperature-aware software-based self-testing for delay faults., , , , and . DATE, page 423-428. ACM, (2015)Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing., , , , and . ASP-DAC, page 514-519. IEEE, (2015)A unified test architecture for on-line and off-line delay fault detections., , and . VTS, page 272-277. IEEE Computer Society, (2011)Non-robust Test Generation for Crosstalk-Induced Delay Faults., , , and . Asian Test Symposium, page 120-125. IEEE Computer Society, (2005)P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework., , , and . Asian Test Symposium, page 117-120. IEEE Computer Society, (2010)An Efficient Algorithm for Finding a Universal Set of Testable Long Paths., , , and . Asian Test Symposium, page 319-324. IEEE Computer Society, (2010)Fast path selection for testing of small delay defects considering path correlations., , , and . VTS, page 3-8. IEEE Computer Society, (2010)Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes., , , , and . DFT, page 298-305. IEEE Computer Society, (2004)