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A unified test architecture for on-line and off-line delay fault detections.

, , and . VTS, page 272-277. IEEE Computer Society, (2011)

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Fast and scalable lock methods for video coding on many-core architecture., , , , , , , , and . J. Visual Communication and Image Representation, 25 (7): 1758-1762 (2014)Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints., , and . ASP-DAC, page 720-725. IEEE, (2014)A High-Precision On-Chip Path Delay Measurement Architecture., , and . IEEE Trans. VLSI Syst., 20 (9): 1565-1577 (2012)Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume., , and . IEEE Trans. VLSI Syst., 20 (12): 2157-2169 (2012)A unified test architecture for on-line and off-line delay fault detections., , and . VTS, page 272-277. IEEE Computer Society, (2011)Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing., , , , and . ASP-DAC, page 514-519. IEEE, (2015)On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island., , , and . VLSI-DAT, page 1-4. IEEE, (2015)A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands., , , and . ACM Trans. Design Autom. Electr. Syst., 21 (2): 27:1-27:14 (2016)A Low Overhead On-Chip Path Delay Measurement Circuit., , and . Asian Test Symposium, page 145-150. IEEE Computer Society, (2009)Corrigendum to "Fast and scalable lock methods for video coding on many-core architecture" J. Visual Communication and Image Representation 25(7) (2014) 1758-1762., , , , , , , , and . J. Visual Communication and Image Representation, (2015)