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Disambiguation of "Gupta, Saket"

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Variation-Aware Variable Latency Design.

, and . IEEE Trans. VLSI Syst., 22 (5): 1106-1117 (2014)

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Shriya Gupta University of Stuttgart

Ratnesh Kumar Gupta University of Stuttgart

 

Other publications of authors with the same name

Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories., , , , , and . IEEE Trans. on Circuits and Systems, 63-I (7): 1014-1022 (2016)BioinQA: metadata-based multi-document QA system for addressing the issues in biomedical domain., , and . IJDMMM, 5 (1): 37-56 (2013)Circuit reliability: From Physics to Architectures: Embedded tutorial paper., , , , , , and . ICCAD, page 243-246. ACM, (2012)Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors., , , , , , and . CICC, page 1-4. IEEE, (2012)Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations., and . IEEE Trans. VLSI Syst., 20 (11): 2104-2117 (2012)Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs., , , , , , , , , and . IRPS, page 2. IEEE, (2015)Variation-Aware Variable Latency Design., and . IEEE Trans. VLSI Syst., 22 (5): 1106-1117 (2014)Employing circadian rhythms to enhance power and reliability., and . ACM Trans. Design Autom. Electr. Syst., 18 (3): 38:1-38:23 (2013)Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs., , , , , and . IRPS, page 4. IEEE, (2018)Current source modeling in the presence of body bias., and . ASP-DAC, page 199-204. IEEE, (2010)