%0 Journal Article %1 journals/tvlsi/GuptaS14 %A Gupta, Saket %A Sapatnekar, Sachin S. %D 2014 %J IEEE Trans. VLSI Syst. %K dblp %N 5 %P 1106-1117 %T Variation-Aware Variable Latency Design. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#GuptaS14 %V 22

@article{journals/tvlsi/GuptaS14, added-at = {2018-11-02T00:00:00.000+0100}, author = {Gupta, Saket and Sapatnekar, Sachin S.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/22cb1d2d5c29645c57371e859914459a9/dblp}, ee = {https://doi.org/10.1109/TVLSI.2013.2265662}, interhash = {798fea138625f90895c35a6114f8232c}, intrahash = {2cb1d2d5c29645c57371e859914459a9}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 5, pages = {1106-1117}, timestamp = {2019-09-27T06:53:40.000+0200}, title = {Variation-Aware Variable Latency Design.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi22.html#GuptaS14}, volume = 22, year = 2014 }