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Computer Aided Testability Evaluation and Test Generation.

, , and . ITC, page 338-345. IEEE Computer Society, (1983)

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System-Diagnosis of Cluster-Based Parallel Architectures., , and . PDP, page 305-309. IEEE Computer Society, (1996)Off-Line Diagnosis of Parallel Systems., and . SRDS, page 360-365. IEEE Computer Society, (1998)Testability Analysis for Software Components., , and . ICSM, page 422-429. IEEE Computer Society, (2002)Impact of hardware emulation on the verification quality improvement., , and . VLSI-SoC, page 218-223. IEEE, (2007)From Design Validation to Hardware Testing: A Unified Approach., and . J. Electronic Testing, 14 (1-2): 133-140 (1999)Towards a unified approach to the testability of co-designed systems., and . ISSRE, page 278-285. IEEE Computer Society, (1995)Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test., , , , and . VLSI Design, (2008)Analyzing Testability on Data Flow Designs., , and . ISSRE, page 162-173. IEEE Computer Society, (2000)Qualification of behavioral level design validation for AMS & RF SoCs., , , , and . VLSI-SoC, page 206-211. IEEE, (2007)A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application., , , , and . NOCS, page 149-158. IEEE Computer Society, (2008)