%0 Conference Paper %1 conf/vlsi/JoannonBRTC07 %A Joannon, Yves %A Beroulle, Vincent %A Robach, Chantal %A Tedjini, Smail %A Carbonéro, Jean-Louis %B VLSI-SoC %D 2007 %I IEEE %K dblp %P 206-211 %T Qualification of behavioral level design validation for AMS & RF SoCs. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#JoannonBRTC07

@inproceedings{conf/vlsi/JoannonBRTC07, added-at = {2008-05-09T00:00:00.000+0200}, author = {Joannon, Yves and Beroulle, Vincent and Robach, Chantal and Tedjini, Smail and Carbonéro, Jean-Louis}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2072789e0cd9bd74909276fc80172c567/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2007soc}, ee = {http://dx.doi.org/10.1109/VLSISOC.2007.4402499}, interhash = {216d2557225e63daf2a0cae3c92c712a}, intrahash = {072789e0cd9bd74909276fc80172c567}, keywords = {dblp}, pages = {206-211}, publisher = {IEEE}, timestamp = {2016-02-02T11:53:53.000+0100}, title = {Qualification of behavioral level design validation for AMS & RF SoCs.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#JoannonBRTC07}, year = 2007 }