%0 Journal Article %1 journals/vlsi/JoannonBRTC08 %A Joannon, Yves %A Beroulle, Vincent %A Robach, Chantal %A Tedjini, Smail %A Carbonéro, Jean-Louis %D 2008 %J VLSI Design %K dblp %P 596146:1-596146:9 %T Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2008.html#JoannonBRTC08 %V 2008

@article{journals/vlsi/JoannonBRTC08, added-at = {2018-11-24T00:00:00.000+0100}, author = {Joannon, Yves and Beroulle, Vincent and Robach, Chantal and Tedjini, Smail and Carbonéro, Jean-Louis}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/28e5f673384735a28fa94c3684b7df151/dblp}, ee = {https://www.wikidata.org/entity/Q58646468}, interhash = {5ed99a47093a662aee0af1448ea891a8}, intrahash = {8e5f673384735a28fa94c3684b7df151}, journal = {VLSI Design}, keywords = {dblp}, pages = {596146:1-596146:9}, timestamp = {2019-09-27T06:27:52.000+0200}, title = {Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2008.html#JoannonBRTC08}, volume = 2008, year = 2008 }