PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Jung, Matthias"

Author of the publication

copydeleteadd this publication to your clipboard
Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling.

, , , , , and . ICPP Workshops, page 15:1-15:8. ACM, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mathias Jung University of Stuttgart

Philipp Junger

Dr. Kerstin Jung University of Stuttgart

Tobias Junginger University of Stuttgart

Univ. -Prof. Dr. -Ing. Hans Christian Jünger University of Stuttgart

 

Other publications of authors with the same name

A Component-Based Architecture for Software Communication Systems.. ECBS, page 36-44. IEEE Computer Society, (2000)An In-DRAM Neural Network Processing Engine., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Exploring system performance using elastic traces: Fast, accurate and portable., , , , and . SAMOS, page 96-105. IEEE, (2016)Improving the error behavior of DRAM by exploiting its Z-channel property., , , , , and . DATE, page 1492-1495. IEEE, (2018)A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing., , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 429-441. Springer, (2019)A Model-Based Safety Analysis of Dependencies Across Abstraction Layers., , , , , , , , , and . SAFECOMP, volume 11093 of Lecture Notes in Computer Science, page 73-87. Springer, (2018)Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs., , , , , , and . ISVLSI, page 609-614. IEEE Computer Society, (2015)Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM., , , and . DAC, page 100:1-100:4. ACM, (2016)System simulation with gem5 and SystemC: The keystone for full interoperability., , , and . SAMOS, page 62-69. IEEE, (2017)Fast validation of DRAM protocols with timed petri nets., , , , , and . MEMSYS, page 133-147. ACM, (2019)