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Bringing C++ productivity to VHDL world: From language definition to a case study., , and . FDL, page 1-7. IEEE, (2011)Exploiting expendable process-margins in DRAMs for run-time performance optimization., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)A High-Performance FPGA-Based Implementation of the LZSS Compression Algorithm., , and . IPDPS Workshops, page 449-453. IEEE Computer Society, (2012)A new bank sensitive DRAMPower model for efficient design space exploration., , , , and . PATMOS, page 283-288. IEEE, (2016)Efficient coding scheme for DDR4 memory subsystems., , , , , , and . MEMSYS, page 148-157. ACM, (2018)ConGen: An Application Specific DRAM Memory Controller Generator., , , , , , and . MEMSYS, page 257-267. ACM, (2016)Reverse Engineering of DRAMs: Row Hammer with Crosshair., , , and . MEMSYS, page 471-476. ACM, (2016)A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture., , , , , and . Signal Processing Systems, 87 (3): 327-341 (2017)Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements., , , , , , and . REDUNDANCY, page 149-154. IEEE, (2019)Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs., , , , , , and . ISVLSI, page 609-614. IEEE Computer Society, (2015)