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Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.

, , , , , and . ISCAS, page 1925-1928. IEEE, (2014)

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Complexity reduction for the 3D-HEVC depth maps coding., , , , and . ISCAS, page 621-624. IEEE, (2015)A complexity reduction algorithm for depth maps intra prediction on the 3D-HEVC., , , , , and . VCIP, page 137-140. IEEE, (2014)A hardware friedly motion estimation algorithm for the emergent HEVC standard and its low power hardware design., , and . ICIP, page 1991-1994. IEEE, (2013)Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder., , , , and . ISVLSI, page 280-285. IEEE Computer Society, (2009)A multilevel data reuse scheme for Motion Estimation and its VLSI design., , , and . ISCAS, page 583-586. IEEE, (2011)Design and FPGA Prototyping of a H.264/AVC Main Profile., , , , , , , , and . J. Braz. Comp. Soc., 13 (1): 25-36 (2007)Performance Analysis of Depth Intra-Coding in 3D-HEVC., , , and . IEEE Trans. Circuits Syst. Video Techn., 29 (8): 2509-2520 (2019)Complexity control of high efficiency video encoders for power-constrained devices., , , and . IEEE Trans. Consumer Electronics, 57 (4): 1866-1874 (2011)A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems., , , , , and . SBCCI, page 31:1-31:6. ACM, (2014)Depth modeling modes complexity control system for the 3D-HEVC video encoder., , , and . EUSIPCO, page 1021-1025. IEEE, (2017)