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Design and FPGA Prototyping of a H.264/AVC Main Profile., , , , , , , , and . J. Braz. Comp. Soc., 13 (1): 25-36 (2007)High throughput architecture for H.264/AVC forward transforms block., , , , , and . ACM Great Lakes Symposium on VLSI, page 320-323. ACM, (2006)A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor., , , and . DSD, page 210-213. IEEE Computer Society, (2005)High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard., , , and . ICECS, page 150-153. IEEE, (2007)Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation., and . DATE, page 224-229. IEEE Computer Society, (2004)Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders., , , , and . LASCAS, page 65-68. IEEE, (2019)Homogeneity and distortion-based intra mode decision architecture for H.264/AVC., , , , , and . ICECS, page 591-594. IEEE, (2010)Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding., , and . ISVLSI, page 115-120. IEEE Computer Society, (2009)High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard., , , , and . ISCAS, IEEE, (2006)Energy-efficient motion estimation with approximate arithmetic., , , , , and . MMSP, page 1-6. IEEE, (2017)