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An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization., , , , , , , , , and . IEEE Trans. Computers, 58 (12): 1654-1667 (2009)Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations., , , , , , , , , and . SiPS, page 463-468. IEEE, (2007)FLAW: FPGA lifetime awareness., , , , and . DAC, page 630-635. ACM, (2006)TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms., , , , , , , , , and . FPL, page 68-73. IEEE, (2007)Exploiting clock skew scheduling for FPGA., , and . DATE, page 1524-1529. IEEE, (2009)Toward Increasing FPGA Lifetime., , , , , , and . IEEE Trans. Dependable Sec. Comput., 5 (2): 115-127 (2008)Thermal-aware reliability analysis for platform FPGAs., , , , and . ICCAD, page 722-727. IEEE Computer Society, (2008)Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs., and . ISVLSI, page 61-66. IEEE Computer Society, (2009)Analog Layout Synthesis: Are We There Yet?. ISPD, page 127. ACM, (2019)A low-power phase change memory based hybrid cache architecture., , , , , , and . ACM Great Lakes Symposium on VLSI, page 395-398. ACM, (2008)