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A Spatial Correlation Model for Shadow Fading in Indoor Multipath Propagation.

, , , and . VTC Fall, page 1-6. IEEE, (2010)

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A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme., , , , , , , , , and 18 other author(s). ISSCC, page 38-40. IEEE, (2012)A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s., , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 52 (1): 250-260 (2017)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 53 (10): 2906-2916 (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)Enhanced Westwood as per Vegas-Based Estimator with Slowstart Threshold for High-Speed Networks., , and . ICCSA Workshops, page 92-99. IEEE Computer Society, (2008)The effect of process variation on device temperature in FinFET circuits., , and . ICCAD, page 747-751. IEEE Computer Society, (2007)O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors., , , and . ISLPED, page 189-192. ACM, (2008)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy., , and . IEEE Trans. VLSI Syst., 18 (5): 787-793 (2010)