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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.

P. Avasare, J. Declerck, M. Glassee, A. Amin, E. Umans, P. Raghavan, and M. Palkovic. IJERTCS, 4 (1): 42-63 (2013)

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Locality optimization in a compiler for wireless applications.J. Absar, P. Raghavan, A. Lambrechts, M. Li, M. Jayapala, and F. Catthoor. Design Autom. for Emb. Sys., 13 (1-2): 53-72 (2009)A multi-threaded coarse-grained array processor for wireless baseband.T. Aa, M. Palkovic, M. Hartmann, P. Raghavan, A. Dejonghe, and L. der Perre. SASP, page 102-107. IEEE Computer Society, (2011)Bias Temperature Instability analysis of FinFET based SRAM cells.S. Khan, I. Agbo, S. Hamdioui, H. Kukner, B. Kaczer, P. Raghavan, and F. Catthoor. DATE, page 1-6. European Design and Automation Association, (2014)Resolving the memory bottleneck for single supply near-threshold computing.T. Gemmeke, M. Sabry, J. Stuijt, P. Raghavan, F. Catthoor, and D. Atienza. DATE, page 1-6. European Design and Automation Association, (2014)System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.P. Agrawal, D. Milojevic, P. Raghavan, F. Catthoor, L. der Perre, E. Beyne, and R. Varadarajan. Embedded Systems Letters, 6 (4): 85-88 (2014)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.H. Kükner, P. Weckx, S. Morrison, J. Franco, M. Toledano-Luque, M. Cho, P. Raghavan, B. Kaczer, D. Jang, K. Miyaguchi and 5 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1039-1051 (2015)An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.B. Sutter, O. Allam, P. Raghavan, R. Vandebriel, H. Cappelle, T. Aa, and B. Mei. Signal Processing Systems, 61 (2): 157-179 (2010)Bias temperature instability analysis in SRAM decoder.S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, and F. Catthoor. ETS, page 1. IEEE Computer Society, (2013)A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.R. Fasthuber, P. Raghavan, L. der Perre, and F. Catthoor. IEEE Trans. VLSI Syst., 23 (10): 1973-1986 (2015)Coarse-Grained Reconfigurable Array Architectures.B. Sutter, P. Raghavan, and A. Lambrechts. Handbook of Signal Processing Systems, Springer, (2013)

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Disambiguation of "Raghavan, Praveen"

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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.

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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.