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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication.

, , , , , , and . IJERTCS, 4 (1): 42-63 (2013)

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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication., , , , , , and . IJERTCS, 4 (1): 42-63 (2013)Algorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards., , , , , , , , , and 2 other author(s). VTC Spring, page 1-5. IEEE, (2012)Hybrid lattice reduction algorithm and its implementation on an SDR baseband processor for LTE., , , , , and . EUSIPCO, page 91-95. IEEE, (2011)A flexible platform architecture for Gbps wireless communication., , , , , , , and . ISSoC, page 1-6. IEEE, (2012)Towards approaching near-optimal MIMO detection performance ONAC-programmable baseband processor., , , , , , and . ICASSP, page 3893-3897. IEEE, (2014)Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor., , , , , , , , , and . IEEE Trans. Signal Processing, 61 (18): 4438-4449 (2013)An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection., , , , , , and . Signal Processing Systems, 85 (1): 5-21 (2016)Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor., , , , , and . ICC, page 1-5. IEEE, (2011)Overview of a Software Defined Downlink Inner Receiver for Category-E LTE-Advanced UE., , , , , , , , , and . ICC, page 1-5. IEEE, (2011)A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited)., , , , , , , , , and 2 other author(s). GlobalSIP, page 1222-1225. IEEE, (2013)