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A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (8): 1228-1239 (2013)Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design., , , and . ASP-DAC, page 707-712. IEEE, (2012)Explicit solution for Queue Length Distribution of M/T-SPH/1 Queue., , and . APJOR, (2014)A voltage calibration technique of electro-optic probing for characterization internal to IC's chip., , , , and . Microelectronics Reliability, 47 (1): 82-87 (2007)DiscMLA: AUC-based discriminative motif learning., , and . BIBM, page 250-255. IEEE Computer Society, (2015)Lithography-aware layout modification considering performance impact., , , and . ISQED, page 437-441. IEEE, (2011)Efficient aerial image simulation on multi-core SIMD CPU., , , and . ICCAD, page 24-31. IEEE, (2013)Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library., , , , , , and . ICCAD, page 186-193. IEEE, (2013)Constrained pattern assignment for standard cell based triple patterning lithography., , , , and . ICCAD, page 178-185. IEEE, (2013)Triple patterning aware detailed placement with constrained pattern assignment., , , , and . ICCAD, page 116-123. IEEE, (2014)