Author of the publication

BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching.

, , , and . DDECS, page 83-88. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Very wide register: an asymmetric register file organization for low power embedded processors., , , , , and . DATE, page 1066-1071. EDA Consortium, San Jose, CA, USA, (2007)BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching., , , and . DDECS, page 83-88. IEEE Computer Society, (2014)Strengthening Property Preservation in Concurrent Real-Time Systems., , , and . RTCSA, page 106-109. IEEE Computer Society, (2006)Automated extraction of scenario sequences from disciplined dataflow networks., , , , and . MEMOCODE, page 47-56. IEEE, (2013)Link-time effective whole-program optimizations., and . Future Generation Comp. Syst., 16 (5): 503-511 (2000)A different approach to high performance computing.. HiPC, page 22-27. IEEE Computer Society, (1997)FP-map-an approach to the functional pipelining of embedded programs., and . HiPC, page 415-420. IEEE Computer Society, (1997)Critical points based register-concurrency autotuning for GPUs., , , , , and . DATE, page 1273-1278. IEEE, (2016)An automated technique to generate relocatable partial bitstreams for Xilinx FPGAs., , , and . FPL, page 1-4. IEEE, (2015)A Unified Model for Analysis of Real-Time Properties., , and . ISoLA (Preliminary proceedings), volume TR-2004-6 of Technical Report, page 220-226. Department of Computer Science, University of Cyprus, (2004)