Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.

J. Wang, N. Gong, L. Hou, X. Peng, R. Sridhar, and W. Wu. Microelectronics Reliability, 51 (9-11): 1498-1502 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Esteban Gongora Bernoske University of Stuttgart

Yuancong Gong University of Stuttgart

Univ. -Prof. Dr. Na Liu University of Stuttgart

Sven-Oliver Nagel University of Stuttgart

Deniz Namli University of Stuttgart

Other publications of authors with the same name

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors.N. Gong, J. Wang, S. Jiang, and R. Sridhar. IEEE Trans. VLSI Syst., 23 (7): 1196-1209 (2015)Low power tri-state register files design for modern out-of-order processors.N. Gong, G. Tang, J. Wang, and R. Sridhar. SoCC, page 323-328. IEEE, (2011)Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation.N. Gong, and R. Sridhar. SoCC, page 19-24. IEEE, (2010)Mitigating Nonlinear Effect of Memristive Synaptic Device for Neuromorphic Computing.J. Fu, Z. Liao, N. Gong, and J. Wang. IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (2): 377-387 (2019)A thermal-aware distribution method of TSV in 3D IC.L. Hou, J. Fu, J. Wang, N. Gong, W. Zhao, and S. Geng. ASICON, page 1-3. IEEE, (2015)Novel CMOS technology compatible nonvolatile on-chip hybrid memory.Z. Yang, J. Wang, L. Hou, and N. Gong. ASICON, page 1-4. IEEE, (2015)Dummy TSV based bit-line optimization in 3D on-chip memory.X. Chen, S. Pourbakhsh, L. Hou, N. Gong, and J. Wang. EIT, page 580-585. IEEE, (2016)Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.J. Wang, N. Gong, L. Hou, X. Peng, R. Sridhar, and W. Wu. Microelectronics Reliability, 51 (9-11): 1498-1502 (2011)Hybrid-cell register files design for improving NBTI reliability.N. Gong, S. Jiang, J. Wang, B. Aravamudhan, K. Sekar, and R. Sridhar. Microelectronics Reliability, 52 (9-10): 1865-1869 (2012)Switching and leakage power modeling for multiple-supply dynamic gate with delay constraining based on wavelet neural networks.J. Wang, W. Wu, N. Gong, L. Zuo, L. Hou, S. Geng, W. Zhang, and D. Gao. IJCNN, page 3240-3243. IEEE Computer Society, (2009)

PUMA

Disambiguation of "Gong, Na"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.

Please choose a person to relate this publication to

Esteban Gongora Bernoske University of Stuttgart

Yuancong Gong University of Stuttgart

Univ. -Prof. Dr. Na Liu University of Stuttgart

Sven-Oliver Nagel University of Stuttgart

Deniz Namli University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Gong, Na"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.

Please choose a person to relate this publication to

Esteban Gongora Bernoske University of Stuttgart

Yuancong Gong University of Stuttgart

Univ. -Prof. Dr. Na Liu University of Stuttgart

Sven-Oliver Nagel University of Stuttgart

Deniz Namli University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.