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Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.

, , , , , and . The Journal of Supercomputing, 21 (2): 131-144 (2002)

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On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification., , , and . Formal Methods in System Design, 2 (1): 45-72 (1993)Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec., , , and . Journal of Systems Architecture, 45 (10): 791-808 (1999)Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications., , and . Parallel Computing, 23 (12): 1811-1837 (1997)Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 6 (6): 992-1005 (1987)Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems., , and . IEEE Trans. Circuits Syst. Video Techn., 8 (6): 719-733 (1998)Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management., , , , , , , , and . VLSI Signal Processing, 21 (3): 185-194 (1999)Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education.. VLSI Design, page 572-577. IEEE Computer Society, (1998)Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation., , , and . ICIP (3), page 985-989. (1998)Space-time chip equalizer receivers for WCDMA forward link with time-multiplexed pilot., , , , , and . VTC Fall, page 1058-1062. IEEE, (2001)Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm., , and . PDPTA, page 1669-1675. CSREA Press, (1999)