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Disambiguation of "Kushida, Keiichi"

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

, , , , , , , , , , , , and . ISSCC, page 132-133. IEEE, (2016)

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Other publications of authors with the same name

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs., , , , , , , and . VLSIC, page 100-101. IEEE, (2012)7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , and 3 other author(s). ISSCC, page 458-459. IEEE, (2009)DFT techniques for memory macro with built-in ECC., , , and . MTDT, page 109-114. IEEE Computer Society, (2005)Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 49 (1): 118-126 (2014)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction., , , , , , , and . ICICDT, page 1-4. IEEE, (2012)A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers., , , , , and . J. Solid-State Circuits, 45 (11): 2341-2347 (2010)