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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

H. Noguchi, K. Ikegami, S. Takaya, E. Arima, K. Kushida, A. Kawasumi, H. Hara, K. Abe, N. Shimomura, J. Ito, S. Fujita, T. Nakada, and H. Nakamura. ISSCC, page 132-133. IEEE, (2016)

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Accurate analysis of substrate sensitivity of active transistors in an analog circuit.S. Takaya, Y. Bando, T. Ohkawa, T. Takaramoto, T. Yamada, M. Souda, S. Kumashiro, T. Mogami, and M. Nagata. ISQED, page 56-61. IEEE, (2011)Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology.T. Tanamoto, S. Takaya, N. Sakamoto, H. Kasho, S. Yasuda, T. Marukame, S. Fujita, and Y. Mitani. CoRR, (2017)SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation.T. Tanamoto, C. Tanaka, S. Takaya, and M. Koyama. CoRR, (2017)A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing.S. Takaya, M. Nagata, A. Sakai, T. Kariya, S. Uchiyama, H. Kobayashi, and H. Ikeda. ISSCC, page 434-435. IEEE, (2013)A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.Y. Bando, S. Takaya, T. Ohkawa, T. Takaramoto, T. Yamada, M. Souda, S. Kumashiro, T. Mogami, and M. Nagata. IEICE Transactions, 94-C (4): 495-503 (2011)Physically Unclonable Function using Initial Waveform of Ring Oscillators.T. Tanamoto, S. Yasuda, S. Takaya, and S. Fujita. CoRR, (2016)Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking.S. Takaya, H. Ikeda, and M. Nagata. IEICE Transactions, 97-C (6): 557-565 (2014)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.H. Noguchi, K. Ikegami, S. Takaya, E. Arima, K. Kushida, A. Kawasumi, H. Hara, K. Abe, N. Shimomura, J. Ito and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors.Y. Bando, S. Takaya, T. Ohkawa, T. Takaramoto, T. Yamada, M. Souda, S. Kumashiro, T. Mogami, and M. Nagata. IEICE Transactions, 95-C (1): 137-145 (2012)Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.T. Marukame, K. Nomura, M. Matusmoto, S. Takaya, and Y. Nishi. ISCAS, page 1-5. IEEE, (2018)

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Disambiguation of "Takaya, Satoshi"

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.