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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.

, , , , , , , , , , and . ISSCC, page 320-321. IEEE, (2013)

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A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , and 1 other author(s). ISSCC, page 320-321. IEEE, (2013)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , and 3 other author(s). ISSCC, page 458-459. IEEE, (2009)A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 49 (1): 118-126 (2014)A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 348-349. IEEE, (2010)A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers., , , , , , , , and . J. Solid-State Circuits, 46 (11): 2545-2551 (2011)DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs., , , , , , , and . ITC, page 164-169. IEEE Computer Society, (2002)