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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology., , , and . I. J. Circuit Theory and Applications, 45 (11): 1647-1659 (2017)A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs., , , and . IEEE Trans. Emerging Topics Comput., 7 (2): 294-300 (2019)A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency., , , and . IEEE Trans. VLSI Syst., 23 (10): 1973-1986 (2015)Coarse-Grained Reconfigurable Array Architectures., , and . Handbook of Signal Processing Systems, Springer, (2013)Compilation Technique for Loop Overhead Minimization., , , , and . DSD, page 419-426. IEEE Computer Society, (2009)Bias Temperature Instability analysis of FinFET based SRAM cells., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Resolving the memory bottleneck for single supply near-threshold computing., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)A multi-threaded coarse-grained array processor for wireless baseband., , , , , and . SASP, page 102-107. IEEE Computer Society, (2011)