PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Craninckx, Jan"

Author of the publication

copydeleteadd this publication to your clipboard
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.

, , , , , , , , , , , , and . ISSCC, page 568-569. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

Isabel Janowsky University of Stuttgart

Hon. -Prof. Dr. Martin Jansen University of Stuttgart

 

Other publications of authors with the same name

A design methodology for fully reconfigurable Delta-Sigma data converters., , and . DATE, page 1379-1384. IEEE, (2009)A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS., , , and . VLSIC, page 1-2. IEEE, (2014)Calibration Method Enabling Low-Cost SDR., , and . ICC, page 4899-4903. IEEE, (2008)An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS., , , , , and . ISSCC, page 238-239. IEEE, (2008)Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy., , , , , , , , , and 3 other author(s). ISSCC, page 568-569. IEEE, (2007)A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors., , , and . ESSCIRC, page 341-344. IEEE, (2012)13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise., , , and . ISSCC, page 250-252. IEEE, (2016)Calibration of Direct-Conversion Transceivers., , , and . J. Sel. Topics Signal Processing, 3 (3): 488-498 (2009)A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS., , , , and . J. Solid-State Circuits, 51 (7): 1593-1606 (2016)A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS., , , , , and . J. Solid-State Circuits, 45 (10): 2116-2129 (2010)