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Disambiguation of "Yoshioka, Kentaro"

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A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller.

, , , , and . IEICE Transactions, 96-A (2): 443-452 (2013)

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Other publications of authors with the same name

An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer., , , , , , , , , and 18 other author(s). J. Solid-State Circuits, 53 (12): 3688-3699 (2018)PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators., , , , , , and . VLSI Circuits, page 263-264. IEEE, (2018)A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller., , , , and . IEICE Transactions, 96-A (2): 443-452 (2013)An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS., , , , and . IEEE Trans. VLSI Syst., 23 (2): 356-368 (2015)Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC., , , , and . J. Solid-State Circuits, 50 (4): 932-945 (2015)A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier., , , and . ISCAS, page 809-812. IEEE, (2013)7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique., , , , and . VLSIC, page 1-2. IEEE, (2014)Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits., , , , , , , , , and . IEEE Trans. VLSI Syst., 27 (11): 2575-2586 (2019)A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC., , , , and . ASP-DAC, page 111-112. IEEE, (2013)A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS., , , , and . J. Solid-State Circuits, 48 (11): 2628-2636 (2013)