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Disambiguation of "Sekimoto, Ryota"

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A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller.

, , , , and . IEICE Transactions, 96-A (2): 443-452 (2013)

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Other publications of authors with the same name

An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator., , , , and . ESSCIRC, page 381-384. IEEE, (2012)An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique., , , , and . ASP-DAC, page 31-32. IEEE, (2014)An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS., , , , and . IEICE Transactions, 96-C (6): 820-827 (2013)A 4-10 bit, 0.4-1 V Power Supply, Power Scalable Asynchronous SAR-ADC in 40 nm-CMOS with Wide Supply Voltage Range SAR Controller., , , , and . IEICE Transactions, 96-A (2): 443-452 (2013)A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC., , , , and . ASP-DAC, page 111-112. IEEE, (2013)A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator., , , and . ESSCIRC, page 471-474. IEEE, (2011)A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator., , and . APCCAS, page 1015-1018. IEEE, (2010)A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS., , , and . J. Solid-State Circuits, 47 (4): 1022-1030 (2012)A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS., , , , and . J. Solid-State Circuits, 48 (11): 2628-2636 (2013)An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS., , , , and . IEEE Trans. VLSI Syst., 23 (2): 356-368 (2015)